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Google delegates AI chip design to – artificial intelligence
Published
5 years agoon
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NewsbotGoogle’s silicon business started delegating AI chip design tasks to artificial intelligence. The move, described in a newly published AI research paper, aims to solve the fundamental problem with creating contemporary AI chips – obsolescence. Industry-standard turnover times mean even the very latest releases aren’t capable of fully leveraging modern AI capabilities. After all, major advances in machine learning and related fields happen on an almost daily basis, whereas designing and mass-producing supporting hardware tends to take years.
Mimicking human chip designers
The solution Google engineers came up with is a new neural network tasked with mimicking efficient component placement in highly advanced AI chips. By automating one of the most challenging aspects of architectural design, Alphabet’s subsidiary is hoping to revolutionize the industry from the ground up, ushering in a new era of futuristic silicon.
Unlike conventional neural networks, the one devised for this problem grows through reinforcement learning. Meaning instead of analyzing vast volumes of data, it starts with limited information and is encouraged to act upon it, i.e. start designing chip module placement plans momentarily. From there, the process is largely iterative in nature as the network keeps churning out designs, realizing its mistakes, and adjusting its practices accordingly.
In other words, it learns just like a human would, except much faster – courtesy of being fueled by a number of supercomputers. Besides computational power advancements, the network was also programmed to value energy efficiency, as per the same paper.
It’s difficult to estimate how soon could this revised methodology yield widespread industry benefits, though Google scientists are unsurprisingly optimistic. According to the top minds behind the initiative, the first results of the project should be observable in a matter of years, starting with the upcoming generations of the Tensor Processing Unit solutions.