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TSMC Future Revealed: 450mm Wafers, 16/10/7nm FinFET, CoWoS




The semiconductor industry influences our lives in more ways than we could ever imagine, and receiving an opportunity to attend a conference where the future is being not only being discussed, but executed – is not an event to miss. Recently, we attended TSMC’s 2013 Technology Symposium, where the company gathered its ecosystem and discussed where the company headed.

Unlike other conferences which typically boast dedicated websites, notes from sessions, presentations and many more, Taiwan Semiconductor Manufacturing Company (TSMC) adopted the typical Taiwanese way of handling things: low-key, no photography, do-not-talk, etc. In a way, this is one of the cornerstones that threaten TSMC and their role of a manufacturing leader. Compared to IntelGlobalFoundries or even its own clients, NvidiaQualcommAMD etc – TSMC is nowhere in terms of brand awareness, and we only get to hear about TSMC when the company is experiencing difficulties, which is unfortunate. We will leave you to conclude what that means for them as a company brand.

The close-chested approach is also a shame, since the company unveiled a sea of innovations and competitive advantages, which will shape the silicon coming out of their fabs for years to come.

Accelerating Investment in R&D, at an All-time High
There’s no doubt that the semiconductor manufacturing is an incredibly expensive business to be in, where the standard OpEx (Operational Expenditure) is measured in the billions of U.S. Dollars. For example, in terms of OpEx, TSMC went from $1.2 billion in 2005 to $3.63 billion in 2012. When we look at CapEx (Capital Expenditure), TSMC went from $2 billion in 2009 to an estimated $9 billion in 2013. Naturally, this covers the cost of building the new plants, which TSMC calls GigaFabs – capable of starting 100,000 wafers per month (wspm).

TSMC is steadly raising their investments in process technology advancements… in 2012, R&D effort alone reached almost US $1.4 Billion.

During the keynote session, Dr. Morris Chang, the company’s founder and Chairman, CEO gave his high-level overview of the company. Dr. Chang stated that his company is the world’s largest manufacturer of logic in the world, as large as “two leading IDMs combined.” We’re not sure whether he was referring to Intel and Samsung, or GlobalFoundries and Samsung, but there’s no denying that TSMC is significantly larger than many other players in the field… combined.

TSMC at glance – 21+2+2 clean room facilities capable of starting several million wafers each and every month. Exact capacity is held a secret.

The money isn’t just disappearing into thin air. TSMC’s executives were quick to point out the example of GIGAFAB 15, which broke ground in 2010, and started revenue shipments and achieved ramp to 50,000 wspm in just two years, and has since then expanded to 100,000 wspm. The company isn’t stopping with the new facilities either, and the post-event conversations were quite interesting. Even though the industry is allegedly contracting in the number of different manufacturers (fabless), the fact of the matter is that the number of manufactured chips has reached record heights, while the expansion of Fabs such as GIGAFAB 15 drove the prices down.

A Good example was TSMC’s own Customer Index versus SOX (Philadelphia Semi Index), which pitched TSMC way higher than industry average – 123.6% vs. low 100% for SOX.

Roadmap ahead
First and foremost, TSMC plans to introduce volume products based on 20nm Planar design (CLN20SOC) over the course of 2013, switching to FinFET with the 2014 arrival of CLN16FF. As TSMC decided to skip on 14nm, the company is going 16nm to 10nm. 2015 will see no new process nodes, while 2016 is scheduled to see the first 10 nanometer process nodes – CLN10FF.

TSMC’s roadmap shows 20nm Planar Transistor technology on track for this year, followed with high-end GPUs and SoC’s manufactured in 16nm FinFET technology next year. 10nm is three years away… on time for Nvidia Volta?

All of these processes are high-performance, while the company is keeping its Low Power roadmap mostly hush hush. Truth to be told, we would not be surprised if, very soon, the Low Power and High Performance nodes simply merge, as High Performance nodes are becoming more and more power aware, and just are able to scale higher. At least, that was the general feeling between TSMC executives that we managed to listen to. When it comes to the 2013 node, N20SOC or CLN20SOC features 2nd generation Gate-Last High-K Metal Gate (HKMG), bringing a 20% improvement in potential clock boost, or a 30% reduction in power. At the same time, the gate density increased by 1.9x. We expect products from AMD, Nvidia and Qualcomm all to utilize N20SOC process to its full extent (given the cost, the question will be who else jumped the gun to become the first adopter to 20nm).

On the other hand, N16FF is progressing nicely, with the “schedule pulled in” – risk production is starting in fourth quarter of this year, meaning we might see the first products in 16nm as soon as mid-2014. Expect a very limited amount of FinFET silicon during 2014, with fully ramped production by the end of the year. N10FF will be a whole another beast, the 2nd Generation FinFET, 4th Gen of HKMG with completely new set of patterning techniques, while increasing the logic density by 1.9x over 16nm, e.g. almost 4x more than 20nm. 10nm is also the first process for which TSMC hopes to switch to Extreme Ultraviolet (EUV).

The future is not silicon?
One of industry worries is what will happen with the limits of silicon as a material are met. TSMC showed slides showing the world’s first Germanium (Ge-based) PMOS FinFET (pFinFET). The time for introduction is set between 7 and 5nm, as the current roadmap implies.

Meet 3D+3D – FinFET Transistors Inspired by the Human Brain Interconnects
Just as every other player in the industry, TSMC is moving towards the FinFET, e.g. 3D transistors rather than conventional planar circuitry. The industry is shifting, and the company wants to be at the forefront of technology – which is not easy, given that most of the research is located within Intel and IBM’s Common Platform Alliance. However, TSMC is making a major shift not in terms of going to FinFETs alone. The company also plans to introduce 3D chip stacking at the same time, a major innovation in silicon design.

What is CoWoS? Xilinx already has prototype FPGAs out, while Nvidia Volta (GPU + Stacked DRAM) is solely based around this new packaging technology.

This approach is called 3D+3D, and is explained as “Si-based Green System Scaling” and “3D Green CMOS + Si wafer-based 3D chip Stacking”. Dr. Jack Sun, VP Research & Development and CTO, TSMC called this a quest for becoming as complex as the human brain. We’re still approximately 15 years from that point, as TSMC estimates we will need a 2nm process node to make such a concept a reality.

450mm Wafer Update – Pilot Line to Arrive in 2016-2017
One of burning subjects in the industry is the upcoming switch to 450mm, or (almost) 18″ wafers. The industry efforts seem to be focused around the Global 450 Consortium (G450C), located at the College of Nanoscale Science and Engineering (CNSE), part of the University of Albany. If you’re not familiar with G450C, all you need to know is that there are no competitors here – this is an industry effort to transition from 300mm to 450mm wafers, further increasing the chip manufacturing capabilities and putting as much chips on the die as possible. G450C members include GlobalFoundries, IBM, Intel, Samsung and TSMC.

TMSC is moving towards 450mm just as the rest of the industry. The question is can Extreme Ultraviolet be ready or not… and TSMC adopted GPU-like, massively parallel approach to EUV litho.

During the presentation, it was said that the final decision on the initial manufacturing process hasn’t been decided yet but it is a decision between 10nm and 7nm processes. Extreme Ultra-Violet (EUV) was mentioned as one of key things for cracking the 450mm code and this space is where TSMC mentioned its competitive advantages with the parallel beam approach. However, the earliest we’re going to see EUV is the 7nm, with the prototype 10nm line being used as a guinea pig.

Overall, the feeling about TSMC is quite positive. While the company typically gets a lot of negative connotations in most of media, the fact of the matter is that the company wafer output is larger than Intel and Samsung combined. This fact alone is easily overlooked, as this engineering-focused company continuously forgets the importance of marketing, PR and financial / technology analysts. One day we might see TSMC opening up and showing its true colors, since their ramp up ability is second to none. Until that day comes, they will (undeservedly) continue to be the scapegoat if their customer messes up the transistor design.

Until then, remember that regardless of the device you use, you will have at least one component manufactured by TSMC – Qualcomm, Nvidia, AMD, Microsoft, Sony and even the almighty Intel – all have components in their line-up with printed (Made In) “TAIWAN” on the die or the packaging.

Original Author: Theo Valich

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