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NVIDIA to launch 7-Billion Transistor Kepler GPGPU “Tesla” Boards on May 14?

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NVIDIA to launch 7-Billion Transistor Kepler GPGPU

Between May 14-17th, NVIDIA will host its GPU Technology Conference in San Jose, CA. A little bird told us to check the session “S0642 -Inside Kepler.” Hosted by Stephen Jones and Lars Nyland, the topic is covering how NVIDIA created a seven billion transistor – which is a majestic record for the biggest logic ASIC i.e. silicon – Kepler GPU, and how the designers focused on extracting the best computing performance.

Before your head starts to wonder “what 7-billion transistor GPU, since GK104 ‘only’ has 3.5 billion,” it is no big secret that the GK104 i.e. GeForce GTX 680 is not the high end GPU silicon from NVIDIA. The name was given due to its performance versus the competition, but the real single-die monster is only coming.

We expect that NVIDIA will launch the part first and foremost as a Tesla GPGPU i.e. GPU Computing parts, since they can easily charge $1000 for the GPU alone, without adding 3/4/6/8/12/16GB of rock-solid GDDR5 memory with Error Checking and Correction. The interest for this GPU in the scientific community is at an all-time high, since according to our sources, NVIDIA expects to sell more Kepler-based Tesla GPGPU boards than it had sold all of the previous generations of Teslas combined.

The session will begin on penultimate day of GTC 2012 – on Wednesday, 5/16 from 2PM to 3:30PM in Hall 1. You can read the session description below:

S0642 – Inside Kepler

Stephen Jones (NVIDIA) , Lars Nyland (NVIDIA)

In this talk, individuals from the GPU architecture and CUDA software groups will dive into the features of the compute architecture for “Kepler” – NVIDIA’s new 7-billion transistor GPU. From the reorganized processing cores with new instructions and processing capabilities, to an improved memory system with faster atomic processing and low-overhead ECC, we will explore how the Kepler GPU achieves world leading performance and efficiency, and how it enables wholly new types of parallel problems to be solved.

Topic Areas: Parallel Programming Languages & Compilers

Level: Beginner

Day: Wednesday, 05/16

Time: 2:00 pm – 3:20 pm

Location: Hall 1

Original Author: Theo Valich


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