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IBM, GlobalFoundries, Samsung to go FinFET, 3D Transistor with 14nm Process




At the Common Platform Technology Forum 2012 held in Santa Clara, CA – Common Platform members announced their intention to switch from planar to FinFET, so called “3D transistors” by the time of introduction of 14nm process node (2014-2015 timeframe).

Anna Hunter, VP Foundry Business, Samsung opens the Common Platform Technology Forum 2012

In a speech by Anna Hunter, Vice President of Foundry Business for Samsung, she expressed her gratitude to planar transistor “which took us through most of our professional lives and beyond” and announced that the members of the alliance will switch to FinFET transistor, which is also known as “3D transistor” in marketing naming convention of a semiconductor giant which shall remain unnamed here.

The alliance will offer FinFET to all of its customers at the 14nm process node, which paired with Fully Depleted Silicon-On-Insulator (FD-SOI) is pairing incredible transistor density with lower power consumption. The problem with the current partially-depleted SOI (PD-SOI) technology is that the pressure needed for SOI insulation to take place is decreasing yields due to pressure on the already strained silicon. When you pressure the strained silicon transistors, they tend to break. This is also the main reason why Common Platform Manufacturing Alliance, manufacturing arm of Common Platform Technology Alliance decided to go “SOI less” and go bulk with the 28nm and 20nm processes.

Furthermore, the FinFET will be combined with chip stacking technology, which in a very high-level overview – will lead to a very different semiconductor products for the world of tomorrow. We will cover the todaý’s event in greater detail as the week unravels.

Original Author: Theo Valich

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