GlobalFoundries produces zero defect wafers

Recently, we took a trip to Dresden to talk with GlobalFoundries executives and visit the clean room facility known as Fab 1 Module 1 [former Fab 36 from AMD days]. We’ll publish a more in-depth coverage in the next day or two but there is one major thing we have to report – even though press relations folk won’t be pleased with us. We spoke with Udo Nothelfer, VP of GlobalFoundries and General Manager of Fab 1, Subramani Kengeri [VP of Design Solutions] as well as partners from AMTC and Open Silicon.

Udo Nothelfer, GM of Fab 1 was certain at the strengths his company can offer in the foundry business

During our clean room tour, in which BSN* had privy to walk around the facility and see everything, including 32nm and 28nm wafers, we also took a good look onto the displays in the facility, looking around at wafers and the results of our somewhat limited inquiry were astonishing, to say the list. We knew that AMD traditionally enjoyed higher yields than the rest of semiconductor industry, including the manufacturing giants such as Intel. In fact, it was a sobering surprise hearing from well respected semiconductor journalists the lack of the yield information from companies in the foundry business, when that information is accessible through analyst firms.

Look and behold – 32nm SOI, 2nd Gen immersion litho, 1st Gen HKMG with a test pattern

Getting back on the subject, we were checking several things – 32nm SOI test pattern, 28nm Bulk test pattern and mass-produced quad-core and sexa-core dies. Even though we only saw couple of hundred wafers, the number of defects was well, surprisingly low and in orders of magnitude better than some other clean room facilities we had privilege visiting. Naturally, we do not have specific information about the overall yields on the parts, as we only saw few hundred out of 35,000 wafer starts per month.

For instance, on 28nm bulk CMOS test sample, we saw three wafers that had several dozen defects, but those defects would still result in a yield substantially higher than what TSMC is able to achieve with its 40nm process [this sadly, confirms the tale of GlobalFoundries being ahead of its customers].

28nm Bulk Silicon with a complex test pattern

Overall, we saw low amount of discarded dies and several hundred “good to go” ones. Naturally, just as if the silicon is perfect does not mean that 100% of the chips from that wafer will come to life. Yet, we were told that the number of working dies per wafer is “industry leading”.

What was interesting was noticing multiple “zero-defect wafers“, i.e. wafers that had 100% yield. We saw multiple 100% yielding wafers with commercial products as well as wafers with less than 10 defects. The term “German precision” definitely applies here. In a world where a transistor is mere 3-7 atoms thick, seeing a zero-defect wafer is still very much surprising. Seeing several hundred billion of perfect transistors, consisting only out of few Si atoms each, one cannot but marvel at the way how semiconductor industry developed. We often take things for granted and discuss about millions and even billions of transistors, but even at what we can freely call the most advanced foundry in the world, defects do happen.

Yes, we did not expect to see a perfect wafer ever, and back at the day, engineers were telling us such thing is borderline impossible. After all, Gene Amdahl’s revolutionary company went bust with the ill-fated idea to put a mainframe processor on a single wafer. Personally, I have the luck of owning a wafer from Trilogy Systems, serving as an everyday reminder that it is “fucking hard” to manufacture complex ASIC designs such as Fermi, as Ujesh Desai of nVidia [in]famously stated during GPU Technology Conference.

Now that GlobalFoundries is decoupled from AMD, the technologies and procedures GlobalFoundries uses are available to its respectable customers and we’re not surprised to see ARM, Qualcomm, STMicro and others coming to GlobalFoundries in droves. After all, if GlobalFoundries can take yield levels of current 45nm SOI process and achieve them on both SOI and Bulk CMOS silicon wafers, a very high bar will be placed for any discussion where high-end chips can safely be manufactured in the future.

Stay tuned.

Author: Theo Valich

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