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AMD Comes Clean on Transistor Numbers With FX, Fusion Processors




Following our expose on the transistor numbers in the Llano and Trinity processors, AMD’s Peter Amos came back to us with an official explanation;

“Beginning in 2012, AMD updated its methodology for transistor counts to ensure consistency. The numbers provided for our recent Trinity launch (and all disclosures moving forward) are based on a flat device count minus de-capacitor cells. The numbers that were provided at last year’s Hot Chips conference were based on flat device + de-cap cells.”

Apparently, the company had one way of calculating the number of transistors of its products such as CPUs, APUs, GPUs, chipsets and the like. With the new transistor count, AMD is no longer counting de-cap cells, but rather flat device, i.e. future FinFET transistors instead of calculating it altogether.

AMD Trinity APU Die: How AMD squeezed 130 million transistors more than on the original Llano APU

According to the recount, Llano APU is consisted out of 1.17 billion transistors and 280 million de-cap cells. Trinity APU is now officially consisted out of 1.3 billion transistors, occupying the same die size as Llano. The company did not disclose the number of de-cap cells, but we believe that they are in 350-450 million range. The interesting bit is the transistor count on the Zambezi, i.e. FX processors. If AMD indeed had two billion transistors in the original flat device + de-cap cells, and 800 million less in the flat-only count, that means the automatic transistor design procedure the company used on Llano and Zambezi is far from optimal. By the same token, the company made great stride forward with the de-cap optimizations, squeezing 130 million transistors and XYZ amount of de-cap cells in the same die size.

Original Author: Theo Valich

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